1. Field of the Invention
The present invention relates to a circuit design device, and particularly relates to a circuit design device for an ASIC that is one type of semiconductor integrated circuits, and to a circuit design device for facilitating a failure analysis.
2. Description of Related Art
Semiconductor integrated circuits manufactured in a manufacturing process of semiconductor integrated circuits include defective products. Thus, the defective products are eliminated in a test process and only non-defective products are shipped. Here, a rate of the non-defective products at this time is referred to as a yield. In order to enhance the yield, it is necessary to clarify a cause for a failure by a failure analysis and improve the manufacturing process.
However, with miniaturization of the semiconductor integrated circuits in recent years, the failure analysis has been becoming more and more difficult. This is because the resolution of a failure analysis device is not high enough for the element size of the miniaturized semiconductor integrated circuit. Conventionally-used failure-analysis devices include optical failure-analysis devices such as an emission microscope, an OBIRCH (Optical Beam Induced Resistance CHange) device, and an LVP (Laser Voltage Probe). However, using light in an infrared region, these optical failure-analysis devices cannot obtain a resolution of sub-microns or smaller due to the effect of a diffraction limit.
Devices having a higher resolution than the optical failure-analysis devices described above include an electron beam (EB) analyzer. To use the EB analyzer, an electron beam should be emitted directly onto a target interconnection to be analyzed. However, in recent years, as the number of interconnection layers has increased, and the target interconnections to be analyzed are often not exposed, application of the EB analyzer is difficult.
Meanwhile, a fault diagnosis of estimating a fault part on the basis of a result of an LSI test, such as a scan test, has been widely used for a semiconductor integrated circuit, especially for an ASIC (Application Specific Integrated Circuit). However, when a fault part includes many equivalent faults, the fault diagnosis cannot identify a true fault part and extracts multiple fault candidates. When multiple fault candidates are extracted, a true fault part needs to be identified from the multiple fault candidates. To this end, target interconnections to be measured need to be exposed by using a focused ion beam (FIB) device. After the interconnection exposure process is performed, measurement using the EB analyzer is carried out. However, if the number of fault candidates is large, then enormous man-hours are necessary, and thus the failure analysis work takes huge time.
As one of designs for testability (DFT) which facilitates a failure analysis, test point insertion (TPI) is known. In TPI, in order to enhance testability (controllability, observability), a register called a test point is inserted into a target circuit to be designed (see Patent Document 1, for example).
Patent Document 1 describes a circuit design system of the present inventor. With the circuit design system described in Patent Document 1, failure analysis can be efficiently improved even with a fewer observation points by setting optimal insertion positions for observation points (test points).    [Patent Document 1] Japanese Patent Application Laid Open No. 2007-122422 (U.S. Patent Application Publication No. US 2008/0091987)
FIG. 3 of Patent Document 1 shows a configuration of the circuit design system. With reference to FIG. 3 of Patent Document 1, the circuit design system includes an input unit 101, a storage unit 103, a circuit placing unit 105, an inter-cell distance extracting unit 107, a fault candidate extracting unit 109, a judgment unit 111, an observation point inserting unit 113, a circuit routing unit 115, and an output unit 117. The judgment unit 111 includes a failure analyticity evaluating unit 119 and an insertion position deciding unit 121. The failure analyticity means ease or facility of the failure analysis.
The operation of the circuit design system is as follows. First, the input unit 101 inputs a netlist NET and stores it in the storage unit 103. A logic circuit has such a configuration that small circuit elements (hereinafter referred to as “cells”) are interconnected through interconnections (hereinafter referred to as “nodes”), and a relation of connection between the circuit elements is described in the netlist NET. Next, the circuit placing unit 105 refers to the netlist NET and performs placement of cell groups. The circuit placing unit 105 stores in the storage unit 103 cell placement data ARR indicating the cell placement, and outputs it to the inter-cell distance extracting unit 107. The inter-cell distance extracting unit 107 refers to the placement data ARR, and extracts and calculates information on the inter-cell distance. The inter-cell distance extracting unit 107 outputs inter-cell distance data DIS indicating the inter-cell distance, to the judgment unit 111.
The fault candidate extracting unit 109 refers to the netlist NET and extracts an equivalent fault group (also referred to as an “equivalent fault class”). An equivalent fault group refers to a group which is formed of multiple fault candidates that are equivalent to each other. In addition, a fault part in the equivalent fault group cannot be identified by measurement from outside. Here, we assume an example where equivalent fault groups G1, G2, . . . , and G1 (I is an integer equal to or greater than 1) are extracted. Each equivalent fault group Gi (i=1, 2, . . . , and I) includes multiple equivalent fault nodes (also referred to as “equivalent fault interconnections”) Ni1, Ni2, . . . , and NiJi. Here, Ji is the number of equivalent fault nodes (hereinafter referred to as the “number of equivalent fault nodes” or the “number of equivalent fault interconnections”) included in the equivalent fault group Gi. The fault candidate extracting unit 109 outputs fault candidate data CAN indicating the extracted equivalent fault groups Gi, to the judgment unit 111.
The judgment unit 111 decides a target node, which is a node into which an observation point is to be inserted, from multiple equivalent fault nodes, on the basis of the fault candidate data CAN and the inter-cell distance data DIS. Specifically, the failure analyticity evaluating unit 119 of the judgment unit 111 calculates a parameter M defined by an equation 1.
                    [                  Equation          ⁢                                          ⁢          1                ]                                                            M        =                              ∑                          i              =              1                        N                    ⁢                                    J              i                        ·                          P              i                                                          (        1        )            
The parameter Pi in the equation 1 represents a probability (hereinafter referred to as “fault probability”) that a single stuck-at fault is included in the equivalent fault group Gi when the single stuck-at fault occurs. The probability of fault occurrence is high in a circuit region where the distance between cells is large, because a node connecting between the cells is also long. Therefore, the fault probability Pi that the single stuck-at fault is included in the equivalent fault group Gi can be estimated by an equation 2, for example.
                    [                  Equation          ⁢                                          ⁢          2                ]                                                                      P          i                =                                            ∑                              j                =                1                                            J                i                                      ⁢                                          L                ij                            /              2                                            L            all                                              (        2        )            
Lall in the equation 2 is a total sum of the lengths of all the nodes included in all the equivalent fault groups Gi (i=1, 2, . . . , and I) or in the entire circuit. In addition, Lij (j=1, 2, . . . , and Ji) represents the interconnection lengths of the equivalent fault nodes Nij included in the equivalent fault group Gi. Here, the failure analyticity evaluating unit 119 can estimate the interconnection lengths Lij by referring to the inter-cell distance data DIS.
With reference to the equation 1, the parameter M is a sum of the parameters Ji·Pi for all the equivalent fault groups Gi (i=1, 2, . . . , and I). In other words, the parameter M represents an average value of the number of equivalent fault nodes in a case where a single stuck-at fault has occurred at any position in the circuit. In order to facilitate a failure analysis, the parameter M, which is the average value of the number of equivalent fault nodes of when a fault occurs, should be reduced. Thus, the parameter M is referred to as failure analysis difficulty. In order to reduce the failure analysis difficulty M and enhance the failure analyticity, observation points should be inserted into suitable positions in the circuit.
The insertion position deciding unit 121 decides an observation point insertion position (i.e., a target node) at which the failure analysis difficulty M decreases. For example, the insertion position deciding unit 121 decides the target node at which the parameter M decreases most significantly.
The equivalent fault group Gi having the largest number of equivalent fault nodes Ji results in a large value for Ji·Pi, and therefore considerably contributes to a value of the parameter M. Thus, the parameter M can be significantly reduced by selecting target nodes from the equivalent fault nodes Nij (j=1, 2, . . . , and Ji) included in the equivalent fault group Gi. The failure analysis difficulty M can be efficiently reduced with a fewer observation points by preferentially inserting observation points into an equivalent fault group whose number of equivalent fault nodes is large.
In contrast, the failure analysis difficulty M can also be reduced efficiently by inserting observation points into the equivalent fault group Gi which has the largest product Ji·Pi of the number of equivalent fault nodes Ji and the fault probability Pi.
The judgment unit 111 decides target nodes into which observation points are to be inserted, as described above, and generates observation point insertion position data PNT indicating the decided target nodes. The observation point inserting unit 113 refers to the netlist NET and the observation point insertion position data PNT, and inserts at least one observation point into the target node. The observation point inserting unit 113 updates the netlist NET as the observation point is inserted.
The circuit design system repeats the above mentioned processes, as necessary. When the insertion process for the required observation points is finished, the circuit routing unit 115 reads out the netlist NET and the placement data ARR from the storage unit 103. The circuit routing unit 115 performs interconnection routing on the basis of the netlist NET and the placement data ARR, generates layout data LAY indicating a layout of a target circuit to be designed, and outputs the layout data LAY to the output unit 117. The output unit 117 outputs the layout data LAY.
With the circuit design system described in Patent Document 1, target nodes are decided based on the number of equivalent fault nodes Ji. For example, it is likely that the probability that a fault occurs in the equivalent fault group Gi having the largest number of equivalent fault nodes Ji is highest in all of the equivalent fault groups. Hence, the target nodes are selected from the equivalent fault group Gi having the largest number of equivalent fault nodes Ji, and observation points are preferentially inserted into the target nodes. Accordingly, an average value (failure analysis difficulty M) of the number of equivalent fault nodes in a case where a single stuck-at fault has occurred at any position in the circuit is reduced efficiently by inserting a fewer observation points.